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The parent document is www.scn.org/~bk269/stan/cmos.html That document explains the procedure and the reasons for selecting the reexamination process. This page depicts:
IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
In re Application of: )
) Docket Number: 88-08.1
Ward D. Parkinson et al. )
) Paper No.
U.S. Patent 4,962,326 )
Issued: October 9, 1990 ) Group Art Unit: 2504
)
Serial No: 07/222,842 ) Examiner: R. Roseen
Filed: July 22, 1988 )
)
For: REDUCED LATCHUP IN PRE- )
CHARGING I/O LINES TO )
SENSE AMP SIGNAL LEVELS )
)
October 20, 1992
Commissioner of Patents and Trademarks
Washington, D.C. 20231
Dear Commissioner:
REQUEST FOR REEXAMINATION
Reexamination of United States Patent 4,962,326, which issued
on October 9, 1990, to Parkinson, et al. is requested under
35 U.S.C. õõ302-307, and under 37 C.F.R. õ1.510. This patent is
still enforceable. A cut copy of the patent in accordance with
37 C.F.R. õ1.510(b) (4) is submitted herewith as Exhibit A.
I. Claims for which Reexamination is Requested
Reexamination is requested of claims 1 and 8 of the subject
patent, in view of U.S. Patent No. 4,028,557 to Wilson (Exhibit B),
U.S. Patent 4,780,850 to Miyamoto, et al. (Exhibit C), and
U.S. Patent 4,903,238 to Miyatake, et al., (Exhibit D), each alone
or in combination with each other. The above references are newly
applied.
II. Statement of Substantial New Questions of Patentability
A. Overview
The Invention
In CMOS integrated circuits, parasitic NPN and PNP bipolar
transistors are formed, in the configuration of a PNPN layer. This
establishes a silicon controlled rectifier (SCR) which results in
destructive latch-up. The latch-up is triggered by voltage
"bumping" and other means, and is particularly a problem when
supply voltage (Vcc) bumps down after I/O lines are floated. The
"bumping" results in a forward bias condition of the CMOS wells,
thereby creating a potential latch-up condition.
In order to avoid such latch-up, the invention lowers the
precharge voltage to I/O lines by a level corresponding to a
threshold potential (Vt) below bias voltage (Vcc). Since supply
potential to transistors in the CMOS n-wells are limited to
Vcc - Vt, the "bumping" required for latch-up is substantially
increased.
Prior Art
It is submitted that claims 1 and 8 of the subject patent are
technically anticipated by the Wilson patent. The Wilson patent
shows an NMOS sense amplifier in which input/output lines are
charged to a potential which is a predetermined potential minus a
transistor threshold potential. The claims as presented in the
issued patent define a semiconductor junction device (claim 1) or
a DRAM array (claim 8) in which a junction device is interposed
between a signal level voltage source and precharge transistors so
that when the signal lines are being precharged, the current for
precharging the signal lines passes through the junction device
(subparagraph b of both independent claims 1 and 8).
Miyamoto, et al., U.S. Patent 4,780,850 and Miyatake, et al.,
U.S. Patent 4,903,238 disclose memories having a potential level
controlling device interposed between the respective I/O lines and
an external potential.
Miyamoto, et al. show a CMOS DRAM, but without a device
interposed between a supply line and an input/output line.
Potential at bit lines is held at a predetermined potential.
Miyatake, et al. disclose a memory array in which a device is
connected between two I/O lines and ground potential.
B. Subject Matter of Claims 1-14
Claims 1-14 include independent claims 1 and 8. Each
independent claim describes signal lines, an equalization
transistor for equalizing precharge signal levels across the signal
lines, a precharge circuit, and a junction device interposed
between a signal level voltage source and precharge transistors so
that when the signal lines are being precharged, the current for
precharging the signal lines passes through the junction device.
Thus, the preferred embodiment is described as a CMOS part and
a circuit which avoids a particular latch-up problem which is
peculiar to CMOS parts which results from the existence of
parasitic NPN and PNP bipolar transistors being formed in the CMOS
process. The claims define a semiconductor circuit device without
expressly limiting the claims to a CMOS circuit.
Dependent claims 2-7 and 9-14 define specific aspects of the
precharge circuitry but do not expressly recite that such aspects
are part of a CMOS device.
It appears that it may be possible to interpret the claims to
include circuitry other than the intended circuitry, including an
NMOS circuit. Thus, while the invention would not perform its
characteristics depicted in Figure 1B, the claims do not expressly
limit the invention to such a CMOS application. Accordingly the
claims could be read to include a circuit in which specific
prevention of latch-up is not desired, and in which latch-up of the
type addressed by the invention is not a problem.
C. Basis for Substantial New Questions of Patentability
The claims of the subject patent in reexamination may not
patentably distinguish over the Wilson patent, alone and in
combination with Miyamoto and/or Miyatake. The claims of the
subject patent do not literally distinguish Wilson's NMOS circuit
in which an I/O node is charged to a potential which is a voltage
source potential minus a transistor threshold potential.
D. Application of Prior Art References to Claims
U.S. Patent 4,962,326 claim 1 Prior Art
In a semiconductor circuit Wilson shows a transistor
device having a signal between Vdd and an I/O line.
generating source, at least two The specification states that
signal lines which are input/output terminal is at a
precharged to signal sensing level of approximately Vdd
levels, a precharge circuit minus one threshold voltage.
which precharges the signal Column 5, lines 34-48.
lines, an equalization
transistor for equalizing the Miyamoto, et al. show I/O lines
precharge signal levels across connected to bit lines by
the signal lines, and a signal transistors.
level voltage source, the
circuit device comprising: Miyatake, et al. show I/O lines
connected to a Vcc by
a) the precharge circuit transistor devices.
including a plurality of
precharge transistors for
conducting current to different
signal lines during said
precharging of the signal lines
in order to precharge voltage
levels;
b) a junction device
interposed between the signal
level voltage source and the
precharge transistors so that
when the signal lines are being
precharged, the current for
precharging the signal lines
passes through said junction
device;
c) the junction device
having a threshold voltage
which is substantially
equivalent to a desired voltage
drop from signal level voltage
to the precharge voltage
levels, thereby lowering
forward bias of the precharge
transistors by providing a
precharge which is at a
threshold voltage below bias
voltage, and reducing
distortion in signal levels of
the signal lines when voltage
at the signal level voltage
source "bumps" downward by
permitting the allowed range of
power supply voltage bumping to
be increased by and amount
equal to said threshold
voltage.
U.S. Patent 4,962,326 claim 8 Prior Art
In a dynamic access memory Wilson shows a transistor
array, which includes an array between Vdd and an I/O line.
of capacitor cells The specification states that
corresponding to memory address input/output terminal is at a
locations, at least two signal level of approximately Vdd
lines which are precharged to minus one threshold voltage.
signal sensing levels, a Column 5, lines 34-48.
circuit for providing signals
corresponding to signal levels Miyamoto, et al. show I/O lines
in ones of the capacitor cells connected to bit lines by
to the signal lines, a transistors.
precharge circuit which
precharged the signal lines, an Miyatake, et al. show I/O lines
equalization transistor for connected to a Vcc by
equalizing the precharge signal transistor devices.
levels across the signal lines,
a signal level voltage source,
the circuit device comprising:
a) the precharge circuit
including a plurality of
precharge transistors for
conducting current to different
signal lines during said
precharging of the signal lines
in order to precharge voltage
levels;
b) a junction device
interposed between the signal
level voltage source and the
precharge transistors so that
when the signal lines are being
precharged, the current for
precharging the signal lines
passes through said junction
device;
c) the junction device having a
threshold voltage which is
substantially equivalent to a
desired voltage drop from
signal level voltage to the
precharge voltage levels,
thereby lowering forward bias
of the precharge transistors by
providing a precharge which is
at a threshold voltage below
bias voltage, and reducing
distortion in signal levels of
the signal lines when voltage
at the signal level voltage
source "bumps"downward by
permitting the allowed range of
power supply voltage bumping to
be increased by and amount
equal to said threshold
voltage.
III. Conclusion
As shown above this Request raises a substantial new question
of patentability of claims 1 and 8 of the subject patent. A
preliminary amendment accompanies this request.
Respectfully submitted,
/ s /
Stanley N. Protigal
Attorney for the Applicants
Registration No. 28,657
208/368-4503
SP/dd
I hereby certify ...
When the Request for Reexamination was submitted, a preliminary amendment was submitted concurrently:
IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
In re Application of: )
) Docket Number: 88-08.1
Ward D. Parkinson et al. )
) Paper No.
U.S. Patent 4,962,326 )
Issued: October 9, 1990 ) Group Art Unit: 2504
)
Serial No: 07/222,842 ) Examiner: R. Roseen
Filed: July 22, 1988 )
)
For: REDUCED LATCHUP IN PRE- )
CHARGING I/O LINES TO )
SENSE AMP SIGNAL LEVELS )
)
October 20, 1992
Commissioner of Patents and Trademarks
Washington, D.C. 20231
Dear Commissioner:
PRELIMINARY AMENDMENT
Prior to examining the subject patent in reexamination on the
merits, please amend the claims as follows:
Skip down to the
Remarks
In reading this, text added by the amendment is italicized, and canceled text appears in [square brackets]. The italicized text should also appear distinctive on Lynx and other non-GUI applications.
In the Claims:
1. In a CMOS semiconductor circuit memory device having a signal generating source, at least two [signal] input/output lines which are precharged to signal sensing levels, a precharge circuit which precharges the [signal] input/output lines, an equalization transistor for equalizing the precharge signal levels across the [signal] input/output lines, a plurality of sense lines which are connected to said I/O lines, and a signal level voltage source, the circuit device comprising:
a) the precharge circuit including a plurality of precharge transistors for conducting current to different [signal] input/output lines during said precharging of the [signal] input/output lines in order to precharge voltage levels;
b) a junction device interposed between the signal level voltage source and the precharge transistors so that when the [signal] input/output lines are being precharged, the current for precharging the [signal] input/output lines passes through said junction device;
c) the junction device having a threshold voltage which is substantially equivalent to a desired voltage drop from signal level voltage to the precharge voltage levels, thereby lowering forward bias of the precharge transistors by providing a precharge which is at a threshold voltage below bias voltage, and reducing distortion in signal levels of the signal lines when voltage at the signal level voltage source "bumps" downward by permitting the allowed range of power supply voltage bumping to be increased by [and] an amount equal to said threshold voltage.
2. The semiconductor device as described in claim 1, further comprising:
when the [signal] input/output lines are being precharged by the precharge transistors, the equalization transistor being gated by signals at the signal level voltage.
3. The CMOS semiconductor device as described in claim 2, further comprising:
said junction device being an n-channel diode which has a threshold voltage corresponding to a desired voltage drop.
4. The CMOS semiconductor device as described in claim 2, further comprising:
said junction device being a transistor connected as a diode, in series with said precharge transistors, and having a threshold voltage corresponding to a desired voltage drop.
5. The CMOS semiconductor device as described in claim 2, further comprising:
a) said junction device being the plurality of precharge transistors for conducting current to different [signal] input/output lines during said precharging of the [signal] input/output lines;
b) [The precharge] said transistors being N-channel transistors having threshold voltages corresponding to the desired voltage drop.
6. The CMOS semiconductor device as described in claim 5, further comprising:
the equalization transistors having n channels which are connected so as to remain fully biased, thereby increasing the voltage "bump" tolerance of the transistors.
7. The CMOS semiconductor device as described in claim 2, further comprising:
the n channels of the equalization transistors being connected so as to remain fully biased, thereby increasing the voltage "bump" tolerance of the transistors.
8. In a dynamic access memory array formed as a CMOS semiconductor device, which includes an array of capacitor cells corresponding to memory address locations, at least two [signal] input/output lines which are precharged to signal sensing levels, a circuit for providing signals corresponding to signal levels in ones of the capacitor cells to the [signal] input/output lines, a precharge circuit which precharged the [signal] input/output lines, an equalization transistor for equalizing the precharge signal levels across the [signal] input/output lines, a plurality of sense lines which are connected to said I/O lines, and a signal level voltage source, the circuit device comprising:
a) the precharge circuit including a plurality of precharge transistors for conducting current to different [signal] input/output lines during said precharging of the [signal] input/output lines in order to precharge voltage levels;
b) a junction device interposed between the signal level voltage source and the precharge transistors so that when the [signal] input/output lines are being precharged, the current for precharging the [signal] input/output lines passes through said junction device;
c) the junction device having a threshold voltage which is substantially equivalent to a desired voltage drop from signal level voltage to the precharge voltage levels, thereby lowering forward bias of the precharge transistors by providing a precharge which is at a threshold voltage below bias voltage, and reducing distortion in signal levels of the [signal] input/output lines when voltage at the signal level voltage source "bumps"downward by permitting the allowed range of power supply voltage bumping to be increased by [and] an amount equal to said threshold voltage.
9. The [semiconductor] device as described in claim 8, further comprising:
the equalization transistor being gated by signals at the signal level voltage.
10. The [semiconductor] device as described in claim 9, further comprising:
said junction device being an n-channel diode which has a threshold voltage corresponding to a desired voltage drop.
11. The [semiconductor] device as described in claim 9, further comprising:
said junction device being a transistor connected as a diode, in series with said precharge transistors, and having a threshold voltage corresponding to a desired voltage drop.
12. The [semiconductor] device as described in claim 9, further comprising:
a) said junction device being [the plurality of precharge] transistors for conducting current to different [signal] input/output lines during said precharging of the [signal] input/output lines;
b) [The precharge] said transistors being N-channel transistors having threshold voltages corresponding to the desired voltage drop.
13. The [semiconductor] device as described in claim 12, further comprising:
the equalization transistors having n channels which are connected so as to remain fully biased, thereby increasing the voltage "bump" tolerance of the transistors.
14. The [semiconductor] device as described in claim 9, further comprising:
the n channels of the equalization transistors being connected so as to remain fully biased, thereby increasing the voltage "bump" tolerance of the transistors.
REMARKS
Favorable consideration of the Reexamination Application, as
amended, is respectfully requested. By this amendment, the claims
have been limited to a CMOS apparatus. As depicted in Figure 1B
and as described in the Abstract, and int eh Specification at
Column 1, lines 19-47, the invention is specific to the avoidance
of latch-up in a CMOS semiconductor memory device. The limitation
of the claims to a CMOS device is believed to better conform the
claims to the invention as originally disclosed.
This amendment further specifies the signal lines as being
input/output lines. This more closely coincides with the
terminology used in the Specification. (See col. 3, line 64 -
col. 4, line 1.)
Claims 5 and 12 have been amended to define the junction
devices as transistors, rather than as the plurality of precharge
transistors. This is believed to more closely coincide with the
description in the Specification and to avoid any ambiguity between
the invention as defined in claims 5 and 12 and the invention as
defined in the claims from which those claims depend.
The above changes are not believed to add new matter, as
support is found in the specification, as described above. This
amendment is believed to further limit the claims by limiting the
apparatus to a CMOS circuit implementation. The use of the
terminology, "input/output line" is believed t be more specific
than the generic term, "signal lines." The amended claims are
therefore believed to also be more limiting, as required by
37 C.F.R. õõ1.121(f) and 1.530(d).
Submission of Substitute Drawings
Proposed substitute drawings are submitted herewith,
containing Figures 3-4. These corrected drawings show the digit
lines 33 as being on the left sides of the transistors of array 31.
The change coincides with the operation of the invention, as
described on column 4, lines 17-26. This can be seen because it is
not possible to pump sense lines to signal levels which occur on a
portion of a circuit which is in fact shorted to the signal lines,
if one is to interpret those signal levels as previously existing
on the portion of the circuit which is shorted to the signal lines.
Therefore, the drawings would be more easily understood if
elements 33 were indicated on the other side of the transistors
depicted in the array 31. The proposed corrections are shown in
red.
Respectfully submitted,
/ s /
Stanley N. Protigal
Attorney for the Applicants
Registration No. 28,657
208/368-4503
SP/dd
I hereby certify ...
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